1. Field of the Invention
The present invention relates to a digital phase control circuit that receives reference clock signals having a prescribed frequency and outputs one or more clock signals in which phase is controlled in units of a prescribed delay difference (resolution) with respect to the reference clock signal.
2. Description of the Related Art
A digital phase control circuit that receives reference clock signals having a prescribed frequency and that outputs one or more clock signals in which phase is controlled in units of a prescribed delay difference (resolution) with respect to the reference clock signal is configured similar to an example of the prior art, digital phase control circuit 100, that is shown in FIG. 1.
This digital phase control circuit 100 of the prior art is configured such that: input selector S1 having four input terminals is connected to delay locked loop DLL1 that includes a voltage-controlled delay line VCDL1 that is composed of ten stages of differential buffers G1-G10 and the differential buffer is a kind of delay buffer; and moreover, output selector S2 is connected to the output of each of differential buffers G1-G10. Delay locked loop DDL1 is composed of: voltage-controlled delay line VCDL1; phase detector PD1; charge pump CP1; and low-pass filter LPF1.
The composition and operation of this prior-art digital phase control circuit is next explained using numerical values.
Clock signals CLK1-4 (reference clocks) of 325.5 MHz (with a period of 3200 ps) in a total of four phases with phase differences of 800 ps are supplied to the four input terminals IN of selector S1. In other words, two clock signals CLK1 and CLK3 having a half-period phase difference (1600 ps) with respect to each other form one differential pair, and similarly, another two clock signals CLK2 and CLK4 having a relative half-period phase difference (1600 ps) form a differential pair.
These clock signals CLK1-CLK4 are controlled in advance by, for example, a phase-locked loop that is not shown in the figure such that the frequencies of the four clock signals CLK1-CLK4 and the phase differences between them (800 ps) are equal and are then supplied to input terminals IN.
Selector S1 selects and extracts a differential pair from the plurality of input terminals IN. In other words, selector S1 selects a pair of differential clock signals from the four types of differential clock signals CLK1-3, CLK3-1, CLK2-4, and CLK4-2, and outputs to voltage-controlled delay line VCDL1 and phase detector PD1.
In a case in which differential clock signals CLK1-3 are selected, clock signal CLK1 is outputted to one of the two output terminals OUT, and clock signal CLK3 is outputted to the other.
The operation is equivalent in cases in which differential clock signals CLK3-1, CLK2-4, or CLK4-2 are selected. However, the output terminals OUT to which differential clock signals CLK1 and CLK3 are outputted when differential clock signals CLK1-3 are selected is the reverse of that for a case in which differential clock signals CLK3-1 are selected. The same relation holds for differential clock signals CLK2-4 and differential clock signals CLK4-2.
The ten stages of differential buffers G1-G10 that make up voltage-controlled delay line VCDL1 each have propagation delay times of 160 ps and are controlled by the feedback control of delay locked loop DLL1 such that their delay times are uniform. The feedback control of delay locked loop DLL1 is carried out as follows:
A clock signal having the total delay of all buffers G1-G10 is outputted from differential buffer G10. In a case in which differential clock signals CLK1-3 are selected by selector S1, for example, phase detector PD1 both receives clock signals CLK1 and CLK3 that have passed through voltage-controlled delay line VCDL1 and have the total delay of all buffers G1-G10 and receives direct clock signals CLK1 and CLK3 (reference clocks) that have not passed through voltage-controlled delay line VCDL1. Phase detector PD1 compares the phases of clock signal CLK1, which has the total delay, and clock signal CLK3 (the reference clock) that precedes passage through voltage-controlled delay line VCDL1, compares the phases of clock signal CLK3 having the total delay and clock signal CLK1 (the reference clock) that precedes passage through voltage-controlled delay line VCDL1, and detects the phase differences. Phase detector PD1 outputs an UP signal to charge pump CP1 if the phase of clock signal CLK1 (CLK3) having the total delay is behind the phase of clock signal CLK3 (CLK1) that precedes passage though voltage-controlled delay line VCDL1; and outputs a DOWN signal to charge pump CP1 if the phase of clock signal CLK1 (CLK3) is ahead. The operation is equivalent for cases in which differential clock signals CLK3-1, CLK2-4 or CLK4-2 are selected by selector S1.
Charge pump CP1 and low-pass filter LPF1 generate control signals such that each buffer maintains a propagation delay time of 160 ps in accordance with the signals from phase detector PD1 and sends these control signals to each of differential buffers G1-G10.
By means of this feedback control, the delay times of the ten stages of buffers in voltage-controlled delay line VCDL1 are kept uniform. In other words, the period of 160 ps×10 stages=1600 ps is constantly corrected in voltage-controlled delay line VCDL1.
Clock signals having a resolution of 160 ps with respect to the reference clocks are outputted from output terminals OUT through the combination of selections of selectors S1 and S2.
Taking for example a case in which differential buffer G5 is selected by selector S2 as the base state, the output delay of delay locked loop DLL1 at this time will be the delay time 160 ps×5 stages=800 ps, if the delay of selectors S1 and S2 is ignored.
In contrast to this base state, the delay becomes 160 ps×6 stages=960 ps if differential buffer G6 is selected by selector S2. In other words, delay (phase) is delayed with respect to the total delay of the basic state at a resolution of 160 ps.
Still further delay of the phase of the clock signal can be realized by selecting, by means of selector S2, a differential buffer having a higher number in delay locked loop DLL1. Conversely, an advance in the phase of the clock signal can be realized by selecting, by means of selector S2, a buffer having a lower number in delay locked loop DLL1. Thus, in digital phase control circuit 100 of the prior-art example, the delay (phase) resolution coincides with the propagation delay time (160 ps) of the buffers in voltage-controlled delay line VCDL1, i.e., resolution is determined by the buffer propagation delay time.
However, the prior art has the following problems:
Since resolution is determined by the propagation delay time of the buffers, the propagation delay time of the differential buffers must be decreased (made high-speed) to obtain a more minute resolution. However, there are limits to the buffer delay time, and currently, constructing buffers having a delay time of less than 50 ps is technologically extremely difficult. There is consequently the problem that a resolution smaller than the propagation delay time of a buffer cannot be obtained. Since the amount of phase control that is necessary for clock recovery for high-speed data of 2.5 Gbps is on the order of 40-50 ps, the realization of a digital phase control circuit that is capable of controlling phase at a resolution of less than 50 ps is crucial for realizing the high-speed data communication that is now being sought.
In addition, since feedback control is effected by delay locked loop DLL1 such that the total delay of all buffers in voltage-controlled delay line VCDL1 matches the delay (1600 ps) of half-period portions of the received reference clocks, the number of inserted buffers must be increased to the extent that resolution is decreased. If the resolution is reduced to ¼, for example, the number of buffers must be increased fourfold. Accordingly, there is the problem of the increase in circuit current required to increase the buffer speed. There is also the problem that power consumption increases due to the additional circuit current needed for the additional buffers. There is the further problem that the area occupied by circuits increases due to the number of additional buffers.
Delay circuits have been disclosed in Japanese Patent Laid-open No. 18304/97 and Japanese Patent Laid-open No. 18305/97 for freely setting resolution and correcting for variations that arise from fabrication and temperature. These inventions involve delay circuits of a path switching type in which delay times are switched by selecting one of a plurality of paths having different delay times. These delay circuits enable the free setting of resolution, which is produced by the time difference between the delay time of a variable delay gate that is controlled by a first delay time compensation unit and the delay time of a variable delay gate that is controlled by a second delay time compensation unit. In addition, variations in resolution are equalized because the delay time generation circuit and paths are arranged in proximity to each other.
In these delay circuits of the path-switching type, however, there is the problem that the number of selectors and the number of buffers in each stage must be increased to raise resolution. The problems of increase in power consumption and increase in the area occupied by circuits caused by increase in the number of buffers cannot be solved in these path-switching delay circuits.
The increase in the number of selectors in particular creates a problem because the harmful effects caused by deviations in switch timing when switching selectors must be prevented.
In these path-switching delay circuits, moreover, although first and second delay time compensation units for controlling delay times are feedback-controlled by a delay locked loop to correct resolution, the delay processing unit (delay time generation circuit) that actually delays clock signals is not feedback-controlled by a delay locked loop and merely receives delay control signals from the first and second delay time compensation units. Thus, when the delay time compensation unit is separated from the delay processing unit and the feedback system for propagating delay control signals is lengthened, there is the problem that variations in resolution (delay time) are produced by the positions of buffers due to the voltage drop of the control signals.
Finally, in these path-switching delay circuits, both the selectors and the clock frequencies for phase comparison must also be changed in order to change resolution. In concrete terms, the frequency of the reference clocks is changed by a PLL in Japanese Patent Laid-open No. 18304/97 and by a synthesizer in Japanese Patent Laid-open No. 18305/97. In other words, these path-switching delay circuits are analog circuits, and clocks of two different frequencies are generated within the same circuit. As a result, not only is there a danger of generating detrimental resonance, but there is the problem that the circuits cannot be applied to devices having a fixed frequency.